RT809H with NAND256W3A BGA63

jbruneaux

Hi,

I've bought a RT809H programmer to read/write some NAND256W3A BGA devices.

The software identify the NAND correctly (see screenshot, in the log window line 003) using the SmartID feature.
Once detected, I select the NAND256W3A@BGA63 device from the list and try to read the NAND. It then fails with an invalid chip ID (see screenshot, in the popup).

When using the NAND_AUTO profile in the device list, then I can correctly read the device (the chip ID is correct), but when trying to write to the NAND, it find all the blocks as bad (I've a batch of devices, all devices act the same, but devices from the same lot mounted on final board do not have bad blocks, only 2 devices had 1 bad block among 100 devices).

I think there a problem in the pinout used for the NAND256W3A@BGA63 profile because it can't even read the chip ID correctly, whereas it can using the NAND_AUTO.

Please can you correct the two problems ? (Maybe correcting the NAND256W3A profile will also fix the badblock detection problem).

Regards, Jerome

shirleyhuang

Hello, sir, to solve your problem, you can click this link http://www.ifix.net.cn/thread-94376-1-1.html to  download the software named RT809H-20190718-Patch.rar, to have a try.

jbruneaux

Hi,

Thanks for your prompt response. I've tested the new version, it now detect the NAND256W3A correctly but I can't write it (it is stuck on 0%, with the STATUS led on the programmer constantly blinking).

Regards, Jerome

shirleyhuang

jbruneaux 2019-7-18 19:53
Hi,

Thanks for your prompt response. I've tested the new version, it now detect the NAND256W3A corr ...

Suggest you do a programmer self-test first, then make sure your chip is good, after that we can make the judgement.

jbruneaux

Hi,

Sorry, it took me some time to do the self test because i didn't had the self-test boards, so I had to build them (using the schematics found here : http://www.ifix.net.cn/thread-60473-1-1.html).

I've run all the 3 tests (following the guide on the same link above), and all 3 are pass. I can send you the screenshots if you need (I didn't do them during the tests).

I've also made a new test. I've tried to write back the file that was read from the device (device is empty) and this works. The problem is when i try to write a binary image (containing our software) to the chip. My file is a 32Mb binary file (exact size is 33554431 bytes, my binary image only contains nand data, not the OOB content, I wan't RT809H software to write ECC in OOB for me using the settings I gave). The dumped files from RT809H software are 34603008 bytes (data + oob should result in a 528 bytes * 65535 pages = 34602480 bytes).

Does the file to write have a specific format ? If so, is there any way to either get the file format (under NDA if needed) or have a tool to convert from a raw binary image to a RT809H compatible image ?

Regards, Jerome

jbruneaux

I made a mistake, in the post above. The 34603008 bytes are the correct size for the nand image with OOB (528bytes * 65536pages). I made my computation using 65535 pages...

Edit : I tried to create an image file of size 34603008 bytes, filled with random data, and it does not work either. I will do some more testing

jbruneaux

Some more tests results :

Using a file with only 0x00s in it, then the software output Bad block detected for every badblock (seems like the badblock information is read into the image file, instead of being read from the actual chip)
Using a file from a dumped valid nand (containing data + oob), the same thing happen (seems like the badblock marker is not looking at the right place for the device. Nand256w3a uses the 5th byte in the OOB to mark bad block). In our DSP (Blackfin) and in the linux code that is used, the ECC for these chips is written in the fist 3 bytes and in the 9th to 11th bytes (3 bytes of ECC per 256 bytes of data). That way, if the software look for a bad block marker at offset 0 (which is a common location for marker, mostly used for large pages NAND) in the dump file (which it should not in my opinion), it will most likely see an value different from 0xFF.

It seems to me that :

* Badblock information should be read from the device at first time writing to a different block
* Badblock information should not be read from the dump file
* Badblock location for small page devices (pages < 2048) should be located at offset 5th in the OOB, except for devices which datasheet gives an other location
* Writing data to a nand should be available in 2 ways : 1/ Raw write (image file therefore contain the data and OOB content) 2/ Data mode : image file only contains pages data, the OOB is computed and written by the software. The latest might be complex to devellop (even if most code is available from the linux source code), because the software would require some advanced settings (ECC algorythm and settings, OOB layout to use).

Please let me know if you can help me at least to write the dumped image from a working product to the new nands (the one containing both pages data and OOB content). This one should work without throwing bad block detection messages.

Regards,

jbruneaux

Another point : I've build a image file with 512 bytes of random data, 16 bytes to 0xFF, and this pattern is repeated 65536 times to make a full image. Writting this image to the device also return bad block errors on all blocks (meaning that the badblock detection is not where I thought in the file.
The other interesting thing is, event if the write fails, if i read the chip afterwards, it is not empty (I mean, the flash content is not all 0xFF as it is when i make a simple 'erase' command. Attached is a screenshot of a dump of the beginning of the readed content after an unsuccessfull write. Seem like a bit pattern or something like that.

Regards, Jerome

shirleyhuang

Hello, sir, may I know what are you running? Do the product or the maintenance? Besides, do you have WeChat account or QQ? If you, we can add each other for convenient communication.

shirleyhuang

About this situation, basically, the algorithm needs to be customized according to the requirements. And it requires know much information about the hardware system and the software system.